My scholarship has focused on the use of hardware adaptability and specialization in tackling scalability and security considerations for modern computing systems. The common motivation across the following three general themes of research is my belief that solving the computing challenges of tomorrow requires a significant redesign of computing systems with a sharper focus on parallelism, security, reliability, and energy efficiency.

For more details on my work please see the Reconfigurable Computing Lab (RCL) page:

  • Reconfigurable Computing - I look into uses of reconfigurable computing as a general enabling technology. Specifically, I focus on the acceleration of various diverse application domains such as cryptography, signal processing, controls, computer vision, and data mining. My research team and I have developed a set of core computing primitives that have allowed us to be flexible when moving from one application domain to another, allowing us to make rapid progress when starting new collaborations as well as adapt to new reconfigurable platforms, tools, and devices as they hit the market in this rapidly progressing field.
  • Security - I study the use of automation and architectural customization to address various aspects of security and trust at the hardware/software interface. Past projects in this area include looking at the role of the operating system and compiler in providing trusted services. Digging deeper, we have looked at modifying the computer architecture to provide secure computation and I/O, with a specific focus on the interaction between the compiler and architecture. We have also explored design methodologies that can reduce the effectiveness of side-channel attacks on hardware/software systems.
  • Computer Architecture and Compilers - I have been working on a wide range of challenges involving the intersection of architecture, compilers, and system software. My specific focus is on performance, power consumption, and reliability issues for embedded and multi-core processors. Along this direction, my collaborators and I have proposed new cache redundancy techniques for increasing chip yield, and new compiler transformations for improving cache performance and energy efficiency.

Recently, I’ve become more active in research related to engineering education as well as engineering diversity and inclusiveness. I am PI on the Electrical, Computer, and Software Engineers as Leaders (ECSEL) project, funded in part by a $5M, multi-institutional NSF S-STEM grant, and am a Co-PI on the Reinventing the Instructional and Departmental Enterprise (RIDE) collaboration, a $2M NSF RED project that aims to transform our department’s processes related to teaching and engineering education. More details can be found at the respective project websites.

I am affiliated with the Center for Cybersecurity Innovation and Outreach (CyIO) at Iowa State University, as well as the Center for Ultra-Scale Computing and Information Security (CUCIS) at Northwestern University.

What my friends and family think I do
What my friends and family think I do for a living.