CprE 381 : Computer Organization and Design
Spring Semester, 2011
Iowa State University
MWF 9:00-9:50am, Howe 1304

Instructor: Morris Chang
Office Hours: MW 10:00-11:00AM - or by appointment
Office Location: 391A Durham
Contact: phone 294-7618, e-mail: morris at iastate.edu

Number of Credits: 4
Prerequisite: CprE 281 or ComS 321

Students with Disabilities: If you have a disability requiring accommodation for this class, please notify the instructor at the beginning of the semester.

Important Notice: The instructor reserves the right to make minor changes to the syllabus.

Course Goals

This course introduces principles of computer organization and design. It will allow understanding of performance evaluation of computers, the principles of designing the hardware/software interface, a simple implementation of MIPS ISA, and a pipelined implementation of MIPS ISA. You will also understand memory hierarchy and I/O devices and interfaces.

Textbook

Computer Organization and Design: The Hardware/Software Interface, 4th edition, 2009, by D. A. Patterson and J. L. Hennessy, Morgan Kaufmann.

Course Outline.

• Introduction to computer organization
• Evaluating performance
• Instruction set design
• Computer arithmetic
• Processor Datapath and Control
• Pipelining
• Memory organization
• Interfacing processors and peripherals
• Advanced Topics

HOMEWORKS

There will be eight assignments dealing with exercises in the textbook or provided by the instructor.  No late assignment will be accepted. Students are responsible to pick up the assignment from the class web page. If you need to make any alternative arrangements, contact the instructor.

LABORATORIES

There will be eleven lab assignments provided by the instructor. Labs completed within the lab time or checked off within the first 10 minutes of the subsequent session will receive 100% credit. After that, lab grades will be penalized 25% per week.

Attendance is mandatory. Failure to attend lab (or be more than 30 minutes late) will penalize the corresponding lab grade by 25%.

PROJECT

There will be one project in which you will design an instruction set (done as part of one homework) and implement it using a pipelined datapath. You will need to demonstrate that the implementation works with test programs that you will write. You will need to write a project report. More details about the project will be given on the project's webpage..

EXAMS

• Exam 1: March 11
• Exam 2:  April  15

Grading