Index

NameLast modifiedSize
Parent Directory  -
02_Binary_Numbers.pptx2025-08-27 14:45 6.5M
03_Logic_Gates.pptx2025-08-29 14:35 3.3M
04_No_Class.pptx2025-08-29 14:38 58K
05_Boolean_Algebra.pptx2025-09-03 15:52 6.2M
06_Synthesis.pptx2025-09-05 15:39 2.1M
07_NAND_and_NOR.pptx2025-09-08 15:20 6.5M
08_Design_Examples.pptx2025-09-10 15:47 7.9M
09_Intro_to_Verilog.pptx2025-09-11 16:56 1.3M
10_K-Maps.pptx2025-09-15 15:19 1.5M
11_Minimization.pptx2025-09-17 15:29 1.4M
12_Functions_and_Circuits.pptx2025-09-19 15:46 2.4M
13_Examples.pptx2025-09-22 15:28 2.5M
14_Midterm_Review.pptx2025-09-22 15:30 59K
15_Midterm1_No_Lecture.pptx2025-09-22 15:31 58K
16_Addition_of_Unsigned_Numbers.pptx2025-09-29 15:15 1.5M
17_Signed_Numbers.pptx2025-10-03 15:02 1.8M
18_Fast_Adders.pptx2025-10-06 18:03 4.9M
19_Multiplication.pptx2025-10-06 15:59 4.9M
20_Floating_Point_Numbers.pptx2025-10-07 21:45 4.1M
21_Multiplexers.pptx2025-10-13 16:09 7.5M
22_Decoders_and_Encoders.pptx2025-10-13 16:09 2.1M
23_Code_Converters.pptx2025-10-15 15:44 5.4M
24_Latches.pptx2025-10-17 15:45 4.2M
25_D_Flip-Flops.pptx2025-10-20 15:15 2.0M
26_T_and_JK_Flip-Flops.pptx2025-10-22 15:36 7.7M
27_Registers.pptx2025-10-24 15:25 2.4M
28_Register_File.pptx2025-10-27 15:53 5.8M
29_Counters.pptx2025-10-29 15:54 1.1M
30_Midterm2_No_Lecture.pptx2025-10-29 15:55 58K
31_Examples_with_Counters.pptx2025-11-03 15:17 2.2M
32_Basic_Design_Steps.pptx2025-11-05 14:25 1.3M
33_State_Assignment_Problem.pptx2025-11-07 14:29 4.0M
34_Mealy_State_Model.pptx2025-11-10 15:59 1.2M
35_Serial_Adder_and_Arbiter_Circuit.pptx2025-11-12 16:02 1.8M
36_Designing_a_Counter.pptx2025-11-14 16:14 1.9M
37_State_Minimization.pptx2025-11-15 00:18 1.1M
38_Analysis_of_SSC.pptx2025-11-15 00:19 1.5M
39_ASM_Charts.pptx2025-11-15 00:20 2.1M
40_Register_Machines.pptx2025-11-29 15:29 614K
41_i281_CPU_Architecture.pptx2025-12-03 16:08 17M
42_Assembly_Language.pptx2025-12-05 16:16 6.0M