Graduate Seminar with Farayola Praise Ololade: Systematic Hardware Error Identification and Calibration for Massive Multisite Testing

Date/Time
Date(s) - 22 Sep 2021
1:10 PM - 2:00 PM

Location
3043 ECpE Building Addition

Speaker: Farayola Praise Ololade, ECpE Graduate Student

Advisor: Degang Chen

Title: Systematic Hardware Error Identification and Calibration for Massive Multisite Testing

Abstract: Multisite testing significantly increases throughput by testing multiple chips simultaneously. When implemented on a large scale (massive multisite), the complex signal routing involved, interference, and coupling on the test hardware (amongst other issues) often affect test sites differently, introducing variations in site measurements. We hypothesize that each test site’s measurement can be modeled as a weak nonlinear function of the true chip measurement with systematic errors. We propose an algorithm to detect these systematic errors and calibrate them.  This approach provides a practical black box technique to mitigate test hardware variations while investigating the fundamental root causes. The proposed method is verified with simulation and real test data.

Bio: Praise O. Farayola (Student Member, IEEE) received the B.Sc. degree in electrical and electronics engineering from the University of Ibadan, Ibadan, Nigeria, in 2015. He is currently pursuing a Ph.D. degree in electrical engineering with Iowa State University, Ames, IA, USA.,In 2020 (summer), he was an Analog Circuit Design Intern with Texas Instruments, Dallas, TX, USA. He worked majorly on current feedback amplifier designs and verification with the High-Speed Operational Amplifier Team, Tucson, Arizona. His research interest includes multisite testing, test hardware error identification and calibration, low-cost high-precision ADC testing, analog circuit design, and fault coverage analysis for analog circuits.

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