Date(s) - 20 Feb 2019
1:10 PM - 2:00 PM
3043 ECpE Building Addition
Speaker: Shravan Chaganti, ECpE Graduate Student
Adviser: Degang Chen
Title: Fast and Accurate Linearity Test for Digital to Analog Converters Using Segmented Models
Abstract: Data converters are critical components of integrated circuits used in control/actuation and sensing applications. If left un-optimized, their production test time often dominates the overall system-on-chip (SoC) test time, leading to high cost of build. In this talk, we will focus on static linearity test of DACs and propose architecture-aware segmented models of non-linearity to minimize test time without compromising test quality. The segmented model, embedded in the uSMILE algorithm, is also modified to account for DACs which have interpolated structures, making the approach applicable to a wide variety of DAC architectures.