Date(s) - 14 Feb 2018
1:10 PM - 2:00 PM
3043 ECpE Building Addition
Speaker: Ankur Sharma, ECpE Graduate Student
Adviser: Chris Chu
Title: Rapid Gate Sizing with Fewer Iterations of Lagrangian Relaxation
Abstract: In digital VLSI circuit optimization gate sizing is one of the most commonly used technique. It can effectively trade-off delay, area and power. Of the several approaches proposed to do gate sizing, Lagrangian Relaxation (LR) based gate sizers have been shown to yield designs with lower leakage power in a timing constrained leakage power minimization type of problem statement. Existing LR based gate sizers however, take many iterations to converge to a competitive solution. In this paper, we propose a novel LR based gate sizer which dramatically reduces the number of iterations while achieving a similar reduction in leakage power and meeting the timing constraints. The decrease in the iteration count is enabled by an elegant Lagrange multiplier update strategy for rapid coarse-grained optimization and finer-grained timing and power recovery techniques, which allow the coarse-grained optimization to terminate early without compromising the solution quality. Since LR iterations dominate the total runtime, our gate sizer achieves an average speedup of 2.5x in runtime and saves 1\% more power compared to the previous fastest work.