Title: Sparse Matrix Vector Multiplication on FPGA-based Platforms
Speaker: Kevin Townsend, ECpE Graduate Student
Advisor: Joseph Zambreno, Associate Professor
Abstract: This dissertation implements a sparse matrix vector multiplication (SpMV) algorithm for FPGAs. CPUs, GPUs, and FPGAs are processors that run different algorithms at different speeds. Much like how the performance of an athlete depends on the design of the course as much as it does on the particular athlete. SpMV is an interesting course in that tweaking the size and sparsity of the matrix will change who wins the race. For example, CPUs compute small matrices quickly due to the fact the matrix and vector can fit in on-chip cache. GPUs compute structured matrices quickly due to how they preprocess the matrix. Currently FPGAs compute matrices at a relatively consistent speed, but we show compressible matrices can achieve better performance. In this paper, we implement an FPGA-based SpMV algorithm and use features of the course to run faster.