Speaker: Sachin Sapatnekar, Chair and University Professor of Electrical and Computer Engineering at the University of Minnesota
Title: How to Age Gracefully (If You’re a Silicon Chip)
Abstract: Performance degradation due to aging is widely recognized to be a serious problem for high-performance integrated circuits. The modeling and optimization of VLSI circuit reliability requires the ability to abstract detailed device and interconnect models into simple, high-fidelity forms that are appropriate for use by the circuit designer. Detailed physics-based models can be too complex for use in large circuits, but simpler, purely empirical models may not provide sufficient insight. This talk describes some of our (ongoing) efforts on linking physics-based models to simulation and optimization techniques that can be scaled to the full-chip level. We consider the notion of parametric and catastrophic failure models and point out that when applied to model circuit failure, these terms can be interchangeable, depending on the circumstances. Next, we illustrate techniques for estimating and enhancing the reliability of large digital circuits. We present methods that can be used during (a) the presilicon stage when the chip is being designed, and (b) the postsilicon stage when the chip is in the field. For presilicon design, methods at the gate level, circuit level, and architectural level are devised to manage delay degradations due to aging by adding timing margins and by developing strategies that minimize these margins. At the postsilicon stage, surrogate sensors such as ring oscillators can be used to predict the performance degradation of an arbitrary circuit block, and then online adaptation methods may be applied to enhance resilience.
Bio: Sachin Sapatnekar received the Ph.D. degree from the University of Illinois at Urbana-Champaign in 1992, after which he joined the faculty at Iowa State University. Since 1997, he has been teaching at the University of Minnesota, where he is a Distinguished McKnight University Professor and the Henle Chair. His research is related to developing CAD techniques for the analysis and optimization of circuit performance, currently focused on both CMOS circuits and spintronics technologies. He has served as Editor-in-Chief of the IEEE Transactions on CAD and General Chair for the ACM/IEEE Design Automation Conference (DAC). He is a recipient of several conference Best Paper Awards, ten-year retrospective Best Paper Awards, the Semiconductor Research Corporation’s Technical Excellence Award, and the Semiconductor Industry Association University Research Award, and a Fulbright award. He is a Fellow of the IEEE and the ACM.