Date(s) - 11 Jun 2018
11:00 AM - 12:00 PM
3043 ECpE Building Addition
Speaker: Ehsan Rohani, Senior Member of VLSI Signal Processing (VLSIP) Lab
Title: The Rewriting of a 50-Year-Old Solution for 5G Integer-Forcing Detectors: Singular Value Decomposition
Abstract: At first, I describe our motivation in improving the performance of Singular Value Decomposition (SVD). After a short survey of previous works I introduce the algorithm and the fixed point hardware to calculate the normalized singular value decomposition of a non-symmetric matrices using Givens fast (approximate) rotations. This algorithm only uses the basic combinational logic modules such as adders, multiplexers, encoders, Barrel shifters (B-shifters), and comparators and does not use any lookup table. This method in fact combines the iterative properties of singular value decomposition method and CORDIC method in one single iteration. The introduced architecture is a systolic architecture that uses two different types of processors, diagonal and non-diagonal processors. The diagonal processor calculates, transmits and applies the horizontal and vertical rotations, while the non-diagonal processor uses a fully combinational architecture to receive, and apply the rotations. The design presented in this work provides 2.83∼649 times better energy per matrix performance compared to the state of the art designs.
Bio: Ehsan Rohani received his B.Sc. with honors in Electronic Engineering from the University of AmirKabir Tehran, Iran. He received his M.Sc. with honors in Electronic Engineering, from the University of Tehran, Iran. Rohani worked on baseband implementation of WiMAX transceiver as his M.Sc. thesis while he was teaching Math, Robotics and Electronics in Tehran schools (2003- 2006). He lectured for undergraduate courses (Electrical Circuits, Electronic Circuits, Logic Circuits, and …) in Islamic Azad University (2006- 2010), and cooperated with Danesh and Honar Institutions (supported by UNICEF). In 2010, Rohani attended the Texas A&M graduate program as a Ph.D. student where he also received the 2015 Outstanding Teaching Assistant Award. Rohani is currently a senior member of VLSI Signal Processing (VLSIP) Lab and he has defended his Ph.D. dissertation on “Hardware Solutions for Next Generation of Telecommunication Systems Physical Layer Implementation.” in December 2016. Rohani’s research interests lie in the area of baseband modeling and implementation of digital communication systems, digital signal processing, bit-true model extraction of digital circuits, computer arithmetic, hardware and software implementation, system simulation, digital filter design, low power techniques for VLSI circuits and DSPs, circuit level design of digital circuits and hardware simulation and implementation of digital systems.