Speaker: Amit Majumdar, DFx Architect at Xilinx
Title: Free to Profile: Device Profiling Anytime
Abstract: Prevailing practice in device profiling is to bin a device at wafer-sort and be done forever. But device characteristics change over time. Much effort has been spent in estimating changes in composite (macro) characteristics such as delay and frequency. But some important parameters cannot be measured past wafer test and thus limits our ability to monitor a chip’s health in the field. This gap is especially important in the context of Automotive and Aerospace reliability requirements. One such metric is device strength (also known as device profiling). The main impediments to such profiling has been technology. Today, device measurements are made on scribe-line test structures using 4-point Kelvin-like equipment. While they provide high accuracy, they are expensive. In this talk, we discuss how to bring these measurements into the die and eliminate external requirements, albeit at the cost of some accuracy. A new use for ring-oscillators (ROs) is proposed by which PMOS and NMOS transistor strengths can be measured and monitored in the field. A new metric, based on RO duty-cycle is defined. This new metric, along with frequency, offers a way to profile and bin transistors based on their drive strengths. With ROs configured from payload transistors, along with the natural programmability of FPGAs, this strength based profiling can be done in the field at a level of granularity that is not possible with existing methodologies. New applications of the metrics and the profiling methodology include use of on-die ROs as a (a) monitor and control for duty-cycle sensitive designs, (b) replacement for scribe-line test structures, and (c) sensor for payload transistor characteristics over life-time.
Bio: Amit Majumdar is the DFx architect in Xilinx, working on testability, debug, characterization and yield aspects of Xilinx’ next generation SoCs. He also spends time working with Xilinx’ software team defining new architectures for debugging applications that are accelerated in Xilinx’ FPGAs. Prior to joining Xilinx, Amit was a Dir. Of Engineering and AMD Fellow in charge of AMD’s GPU DFx activities. He joined AMD after spending a few years at a startup (Startosphere Solutions) working on technologies for extracting, modeling and using fine-grain device data for statistical circuit characterization. Prior to that Amit held architect and management positions at Sun Microsystems, working on CPU DFx. He came to Sun after doing alternating stints at EDA and chip design in companies such as Viewlogic (acquired by Synopsys), Apple and Crosscheck Technologies. Amit started his career in academia as an Assistant Professor in the EE department in Southern Illinois University – Carbondale. He is serving as Program Co-chair for VLSI Test Symposium in 2017 and 2018 and has served as Technical Program Committee member for various conferences and workshops such as VTS, IOLTS, MSTW, ART. Amit received his Bachelor in EE from BITS-Pilani, an MS in ECE from Univ. of Massachusetts, Amherst and a PhD in EE from Univ. of Southern Cal. His research interests range from analog DFx to pattern matching to machine learning and security.