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This work is supported in part by the National Science Foundation (NSF), under awards DUE-1565130, EEC-1623125, CNS-1645987, CNS-1116810, CCF-1149539, CNS-1060337, and CNS-0934725, and by the Air Force Office of Scientific Research (AFOSR), under awards FA9550-11-1-0343 and FA9550-09-1-0194.

Books and Book Chapters

  1. A. Pande and J. Zambreno. Embedded Multimedia Security Systems, Springer-Verlag, London, 146 pages, 2013.

Journal Papers

  1. C. Nelson, K. Townsend, O. Attia, P. Jones and J. Zambreno, "RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing", IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27, no. 10, 2016. [PDF]
  2. X. Wang, P. Jones and J. Zambreno, "A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns", ACM Computer Architecture News (CAN), vol. 43, no. 4, 2015. [PDF]
  3. T. Johnson, D. Roggow, P. Jones and J. Zambreno, "An FPGA Architecture for the Recovery of WPA/WPA2 Keys", Journal of Circuits, Systems, and Computers (JCSC), vol. 24, no. 7, 2015. [PDF]
  4. M. Monga, D. Roggow, M. Karkee, S. Sun, L. K. Tondehal, B. Steward, A. Kelkar and J. Zambreno, "Real-time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform", Microprocessors and Microsystems, vol. 39, no. 8, pp. 720-740, 2015. [PDF]
  5. O. Attia, K. Townsend, P. Jones and J. Zambreno, "A Reconfigurable Architecture for the Detection of Strongly Connected Components", ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 9, no. 2, 2015. [PDF]
  6. K. Townsend, O. Attia, P. Jones and J. Zambreno, "A Scalable Unsegmented Multi-port Memory for FPGA-based Systems", International Journal of Reconfigurable Computing (IJRC), vol. 2015, December, 2015. [PDF]
  7. C. Kumar, S. Vyas, R. Cytron, C. Gill, J. Zambreno and P. Jones. "Hardware-Software Architecture for Priority Queue Management in Real-time and Embedded Systems", International Journal of Embedded Systems (IJES), vol. 6, no. 4, pp. 319-334, 2014. [PDF]
  8. S. Vyas, C. Kumar, J. Zambreno, C. Gill, R. Cytron and P. Jones. "An FPGA-based Plant-on- Chip Platform for Cyber-Physical System Analysis", IEEE Embedded Systems Letters (ESL), vol. 6, no. 1, pp. 4-7, 2014. [PDF]
  9. A. Pande, S. Chen, P. Mohapatra and J. Zambreno. "Hardware Architecture for Video Authentication using Sensor Pattern Noise", IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), vol. 24, no. 1, pp. 157-167, 2014. [PDF]
  10. S. Vyas, A. Gupte, C. Gill, R. Cytron, J. Zambreno, and P. Jones. "Hardware Architectural Support for Control Systems and Sensor Processing", ACM Transactions on Embedded Computing Systems (TECS), vol. 13, no. 2, 2013. [PDF]
  11. A. Pande, P.Mohapatra, and J. Zambreno. "Securing Multimedia Content using Joint Compression and Encryption", IEEE MultiMedia (MM), vol. 20, no. 4, pp. 50-61, 2013. [PDF]
  12. A. Pande and J. Zambreno. "A Chaotic Encryption Scheme for Real-time Embedded Systems: Design and Implementation", Telecommunication Systems, vol. 52, no. 2, pp. 551-561, 2013. [PDF]
  13. A. Pande, J. Zambreno, and P. Mohapatra. "Comments on 'Arithmetic Coding as a Non- Linear Dynamical System'", Communications in Nonlinear Science and Numerical Simulation (CNSNS), vol. 17, no. 12, pp. 4536-4543, 2012. [PDF]
  14. A. Pande and J. Zambreno. "Poly-DWT: Polymorphic Wavelet Hardware Support For Dynamic Image Compression", ACM Transactions on Embedded Computing Systems (TECS), vol. 11, no. 1, 2012. [PDF]
  15. S. Sun, M. Monga, P. Jones, and J. Zambreno. "An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs", IEEE Transactions on Circuits and Systems-I (TCAS-I), vol. 59, no. 1, pp. 113-123, 2012. [PDF]
  16. S. Sun and J. Zambreno. Design and Analysis of a Reconfigurable Platform for Frequent Pattern Mining", IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 22, no. 9, pp. 1497-1505, 2011. [PDF]
  17. A. Pande and J. Zambreno. "Efficient Mapping and Acceleration of AES on Custom Multi-Core Architectures", Concurrency and Computation: Practice and Experience, vol. 23, no. 4, pp. 372-389, 2011. [PDF]
  18. A. Baumgarten, M. Steffen, M. Clausman, and J. Zambreno. "A Case Study in Hardware Trojan Design and Implementation", International Journal of Information Security (IJIS), vol. 10, no. 1, pp. 1-14, 2011. [PDF]
  19. A. Pande and J. Zambreno. "Reconfigurable Hardware Implementation of a Modified Chaotic Filter Bank Scheme", International Journal of Embedded Systems (IJES), vol. 4, no. 3, pp. 248-258, 2010. [PDF]
  20. A. Pande and J. Zambreno. "The Secure Wavelet Transform", Springer Journal of Real-Time Image Processing (RTIP), 2010. [PDF]
  21. A. Baumgarten, A. Tyagi, and J. Zambreno. "Preventing Integrated Circuit Piracy using Reconfigurable Logic Barriers", IEEE Design and Test of Computers, vol. 27, no. 1, pp. 66-75, January 2010. [PDF]
  22. G. Bloom, B. Narahari, R. Simha, and J. Zambreno. "Providing Secure Execution Environments with a Last Line of Defense against Trojan Circuit Attacks", Computers and Security, vol. 28, no. 7, pp. 660-669, October 2009. [PDF]
  23. S. Sun, Z. Yan, and J. Zambreno. "Demonstrable Differential Power Analysis Attacks on Real-World FPGA-Based Embedded Systems", Integrated Computer-Aided Engineering vol. 16, no. 2, pp. 119-130, April 2009.
  24. J. Sathre and J. Zambreno. "Automated Software Attack Recovery using Rollback and Huddle", Springer Journal of Design Automation for Embedded Systems (DAES), vol. 12, no. 3, pp. 243-260, September 2008. [PDF]
  25. D. Nguyen, A. Das, J. Zambreno, G. Memik, and A. Choudhary. "An FPGA-Based Network Intrusion Detection Architecture", IEEE Transactions on Information Forensics and Security (TIFS), vol. 3, no. 1, pp. 118-132, March 2008. [PDF]
  26. A. Das, S. Ozdemir, G. Memik, J. Zambreno, and A. Choudhary. "Microarchitectures for Managing Chip Revenues under Process Variations", IEEE Computer Archiecture Letters, vol. 6, no. 2, pp. 29-32, July 2007. [PDF]
  27. J. Zambreno, D. Honbo, A. Choudhary, R. Simha, and B. Narahari. "High-Performance Software Protection using Reconfigurable Architectures", Proceedings of the IEEE, vol. 94, no. 2, pp. 1-13, February 2006. [PDF]
  28. J. Zambreno, A. Choudhary, R. Simha, B. Narahari, and N. Memon. "SAFE-OPS: An Approach to Embedded Software Security", ACM Transactions on Embedded Computing Systems (TECS), vol. 4, no. 1, pp. 189-210, February 2005. [PDF]

Conference and Workshop Papers

  1. C. Young, J. Zambreno, and G. Bloom, "Towards a Fail-Operational Intrusion Detection System for In-Vehicle Networks", Proceedings of the Workshop on Security and Dependability of Critical Embedded Real-Time Systems (CERTS), November, 2016. [PDF]
  2. X. Zhu, M. Awatramani, D. Rover, and J. Zambreno, "ONAC: Optimal Number of Active Cores Detector for Energy Efficient GPU Computing", Proceedings of the International Conference on Computer Design (ICCD), October, 2016. [PDF]
  3. X. Wang and J. Zambreno, "Parallelizing Latent Semantic Indexing Using an FPGA-based Architecture", Proceedings of the International Conference on Computer Design (ICCD), October, 2016. [PDF]
  4. D. Rover, J. Zambreno, M. Mina, P. Jones, and L. Chrystal, "Evidence-Based Planning to Broaden the Participation of Women in Electrical and Computer Engineering", Proceedings of the Frontiers in Education Conference (FIE), October, 2016. [PDF]
  5. A. Mills, P. Jones, and J. Zambreno, "Parameterizable FPGA-based Kalman Filter Coprocessor using Piecewise Affine Modeling", Proceedings of the Reconfigurable Architectures Workshop (RAW), May, 2016. [PDF]
  6. O. Attia, A. Grieve, K. Townsend, P. Jones and J. Zambreno, "Accelerating All-Pairs Shortest Path Using A Message-Passing Reconfigurable Architecture", Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), December, 2015. [PDF]
  7. P. Zhang, A. Mills, J. Zambreno and P. Jones, "A Software Configurable and Parallelized Coprocessor Architecture for LQR Control", Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), December, 2015. [PDF]
  8. A. Mills, P. Zhang, S. Vyas, J. Zambreno and P. Jones, "A Software Configurable Coprocessor-Based State-Space Controller", Proceedings of the International Symposium on Field-Programmable Logic and Applications (FPL), September, 2015. [PDF]
  9. M. Awatramani, X. Zhu, J. Zambreno and D. Rover, "Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications", Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), October, 2015. [PDF]
  10. X. Wang, P. Jones and J. Zambreno, "A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns", Proceedings of the International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), June, 2015. [PDF]
  11. D. Roggow, P. Uhing, P. Jones and J. Zambreno, "A Project-Based Embedded Systems Design Course Using a Reconfigurable SoC Platform", Proceedings of the International Conference on Microelectronic Systems Education (MSE), May, 2015. [PDF]
  12. K. Townsend, S. Sun, T. Johnson, O. Attia, P. Jones and J. Zambreno, "k-NN Text Classifi- cation using an FPGA-Based Sparse Matrix Vector Multiplication Accelerator", Proceedings of the IEEE International Conference on Electro/Information Technology (EIT), May, 2015. [PDF]
  13. K. Townsend and J. Zambreno, "A Multi-Phase Approach to Floating-Point Compression", Proceedings of the IEEE International Conference on Electro/Information Technology (EIT), May, 2015. [PDF]
  14. A. Mills and J. Zambreno, "Estimating State of Charge and State of Health of Rechargable Batteries on a Per-Cell Basis", Proceedings of the Workshop on Modeling and Simulation of Cyber-Physical Energy Systems (MSCPES), April, 2015. [PDF]
  15. K. Townsend, P. Jones and J. Zambreno. "A High Performance Systolic Architecture for k-NN Classification", Proceedings of the International Conference on Formal Methods and Models for Codesign (MEMOCODE), October 2014. [PDF]
  16. C. Kumar, S. Vyas, R. Cytron, C. Gill, J. Zambreno, and P. Jones. "Cache Design for Mixed Critical Real-Time Systems", Proceedings of the International Conference on Computer Design (ICCD), October 2014. [PDF]
  17. M. Awatramani, D. Rover and J. Zambreno. "Perf-Sat: Runtime Detection of Performance Saturation for GPGPU Applications", Proceedings of the International Workshop on Scheduling and Resource Management for Parallel and Distributed Systems (SRMPDS),September 2014. [PDF]
  18. X. Wang, P. Jones and J. Zambreno. "A Reconfigurable Architecture for QR Decomposition Using A Hybrid Approach", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2014. [PDF]
  19. A. Mills and J. Zambreno. "Towards Scalable Monitoring and Maintenance of Rechargeable Batteries", Proceedings of the IEEE International Conference on Electro/Information Technology (EIT), June 2014. [PDF]
  20. X. Wang and J. Zambreno, "An FPGA Implementation of the Hestenes-Jacobi Algorithm for Singular Value Decomposition", Proceedings of the Reconfigurable Architectures Workshop (RAW), May 2014. [PDF]
  21. O. Attia, T. Johnson, K. Townsend, P. Jones and J. Zambreno. "CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search", Proceedings of the Reconfigurable Architectures Workshop (RAW), May 2014. [PDF]
  22. X. Wang and J. Zambreno. "An Efficient Architecture for Floating-Point Eigenvalue Decomposition", Proceedings of the International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2014. [PDF]
  23. A. Krishna, J. Zambreno, and S. Krishnan. "Polarity Trend Analysis of Public Sentiment on YouTube", Proceedings of the International Conference on Management of Data (COMAD), December 2013. [PDF]
  24. M. Awatramani, J. Zambreno, and D. Rover. "Increasing GPU Throughput using Kernel Interleaved Thread Block Scheduling", Proceedings of the International Conference on Computer Design (ICCD), October 2013. [PDF]
  25. K. Townsend and J. Zambreno. "Reduce, Reuse, Recycle (R^3): a Design Methodology for Sparse Matrix Vector Multiplication on Reconfigurable Platforms", Proceedings of the International Conference on Application-specific Systems, Architectures, and Processors (ASAP), June 2013. [PDF]
  26. C. Kumar, S. Vyas, R. Cytron, C. Gill, J. Zambreno, and P. Jones. "Scheduling Challenges in Mixed Critical Real-time Heterogeneous Computing Platforms", Proceedings of Dynamic Data Driven Application Systems (DDDAS), June 2013. [PDF]
  27. M. Patterson, A. Mills, R. Scheel, J. Tillman, E. Dye, and J. Zambreno. "A Multi-Faceted Approach to FPGA-Based Trojan Circuit Detection", Proceedings of the IEEE VLSI Test Symposium (VTS), April 2013. [PDF]
  28. A. Mills, S. Vyas, M. Patterson, C. Sabotta, P. Jones, and J. Zambreno. "Design and Evaluation of a Delay-Based FPGA Physically Unclonable Function", Proceedings of the International Conference on Computer Design (ICCD), September 2012. [PDF]
  29. C. Nelson, K. Townsend, B. S. Rao, P. Jones, and J. Zambreno. "Shepard: A Fast Exact Match Short Read Aligner", Proceedings of the International Conference on Formal Meth- ods and Models for Codesign (MEMOCODE), July 2012. [PDF]
  30. C. Kumar, S. Vyas, J. Shidal, R. Cytron, C. Gill, J. Zambreno and P. Jones, "Improving System Predictability and Performance via Hardware Accelerated Data Structures", Proceedings of Dynamic Data Driven Application Systems (DDDAS), June, 2012. [PDF]
  31. M. Monga, M. Karkee, L. K. Tondehal, B. Steward, A. Kelkar and J. Zambreno, "Real-Time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform", Proceedings of the International Conference on Computational Science (ICCS), June, 2012. [PDF]
  32. M. Steffen and J. Zambreno, "Exposing High School Students to Concurrent Programming Principles using Video Game Scripting Engines", Proceedings of the Annual Conference of the American Society for Engineering Education (ASEE), June, 2012.
  33. M. Steffen, P. Jones and J. Zambreno, "Introducing Graphics Processing from a Systems Perspective: A Hardware / Software Approach", Proceedings of the Annual Conference of the American Society for Engineering Education (ASEE), June, 2012.
  34. A. Pande, P. Mohapatra, and J. Zambreno. "Using Chaotic Maps for Encrypting Image and Video Content", Proceedings of the International Symposium on Multimedia (ISM), December 2011. [PDF]
  35. J. Rilling, D. Graziano, J. Hitchcock, T. Meyer, X. Wang, P. Jones, and J. Zambreno. "Circumventing a Ring Oscillator Approach to FPGA-Based Hardware Trojan Detection", Proceedings of the International Conference on Computer Design (ICCD), October 2011. [PDF]
  36. A. Pande, J. Zambreno, and P. Mohapatra. "Hardware Architecture for Simultaneous Arithmetic Coding and Encryption", Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), July 2011. [PDF]
  37. A. Pande, J. Zambreno, and P. Mohapatra. "Architectures for Simultaneous Coding and Encryption using Chaotic Maps", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2011. (poster paper) [PDF]
  38. M. Steffen, P. Jones, and J. Zambreno. "Teaching Graphics Processing and Architecture using a Hardware Prototyping Approach", Proceedings of the International Conference on Microelectronic Systems Education (MSE), June 2011. [PDF]
  39. M. Steffen and J. Zambreno. "Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels", Proceedings of the International Symposium on Microarchitecture (MICRO), pp. 237-248, December 2010. [PDF]
  40. A. Pande, J. Zambreno, and P. Mohapatra. "Joint Video Compression and Encryption using Arithmetic Coding and Chaos", Proceedings of the IEEE International Conference on Internet Multimedia Systems Architecture and Applications (IMSAA), December 2010. [PDF]
  41. A. Pande and J. Zambreno. "Design and Hardware Implementation of a Chaotic Encryption Scheme for Real-Time Embedded Systems", Proceedings of the IEEE Signal Processing and Communications Conference (SPCOM), July 2010. [PDF]
  42. M. Steffen and J. Zambreno. "A Hardware Pipeline for Accelerating Ray Traversal Algorithms on Streaming Processors", Proceedings of the IEEE Symposium on Application Specific Processors (SASP), June 2010. [PDF]
  43. M. Karkee, M. Monga, B. Steward, J. Zambreno, and A. Kelkar. "Real-Time Simulation and Visualization Architecture with Field Programmable Gate Array (FPGA) Simulator", Proceedings of the ASME World Conference on Innovative Virtual Reality (WINVR), May 2010.
  44. A. Das, G. Memik, J. Zambreno, and A. Choudhary. "Detecting/Preventing Information Leakage on the Memory Bus due to Malicious Hardware", Proceedings of Design, Automation, and Test in Europe (DATE), March 2010. [PDF]
  45. H. Chen, S. Sun, D. Aliprantis, and J. Zambreno. "Dynamic Simulation of DFIG Wind Turbines on FPGA Boards", Proceedings of the Power and Energy Conference at Illinois (PECI), pp. 39-44, February 2010. [PDF]
  46. A. Pande and J. Zambreno. "A Reconfigurable Architecture for Secure Multimedia Delivery", Proceedings of the International Conference on VLSI Design (VLSID), January 2010. [PDF]
  47. S. Sun and J. Zambreno. "A Floating-point Accumulator for FPGA-based High Performance Computing Applications", Proceedings of the International Conference on Field-Programmable Technology (FPT), December 2009. [PDF]
  48. E. Leontie, G. Bloom, B. Narahari, R. Simha, and J. Zambreno. "Hardware-enforced Fine-grained Isolation of Untrusted Code", Proceedings of the Workshop on Secure Execution of Untrusted Code (SecuCode), November 2009. [PDF]
  49. J. Sathre, A. Baumgarten, and J. Zambreno. "Architectural Support for Automated Software Attack Detection, Recovery, and Prevention", Proceedings of the International Conference on Embedded and Ubiquitous Computing (EUC), August 2009. [PDF]
  50. A. Pande and J. Zambreno. "Efficient Translation of Algorithmic Kernels on Large-Scale Multi-Cores", Proceedings of the International Workshop on Reconfigurable and Multicore Embedded Systems (WoRMES), August 2009. [PDF]
  51. E. Leontie, G. Bloom, B. Narahari, R. Simha, and J. Zambreno. "Hardware Containers for Software Components: A Trusted Platform for COTS-Based Systems", Proceedings of the International Symposium on Trusted Computing and Communications (TrustCom), August 2009. [PDF]
  52. M. Steffen and J. Zambreno. "Design and Evaluation of a Hardware Accelerated Ray Tracing Data Structure", Proceedings of Theory and Practice of Computer Graphics (TPCG), June 2009. [PDF]
  53. A. Pande and J. Zambreno. "An Efficient Hardware Architecture for Multimedia Encryption and Authentication using the Discrete Wavelet Transform", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 85-90, May 2009. [PDF]
  54. H. Chen, S. Sun, D. Aliprantis, and J. Zambreno. "Dynamic Simulation of Electric Machines on FPGA Boards", Proceedings of the International Electric Machines and Drives Conference (IEMDC), May 2009. [PDF]
  55. S. Sun, M. Steffen, and J. Zambreno. "A Reconfigurable Platform for Frequent Pattern Mining", Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2008. [PDF]
  56. A. Das, B. Ozisikyilmaz, S. Ozdemir, G. Memik, J. Zambreno, and A. Choudhary. "Evaluating the Effects of Cache Redundancy on Profit", Proceedings of the International Symposium on Microarchitecture (MICRO), pp. 388-398, November 2008. [PDF]
  57. S. Sun and J. Zambreno. "Mining Association Rules with Systolic Trees", Proceedings of the International Conference on Field-Programmable Logic and its Applications (FPL), pp. 143-148, September 2008. [PDF]
  58. A. Pande and J. Zambreno. "Polymorphic Wavelet Architectures using Reconfigurable Hardware", Proceedings of the International Conference on Field-Programmable Logic and its Applications (FPL), pp. 471-474, September 2008. (poster paper) [PDF]
  59. A. Pande and J. Zambreno. "Design and Analysis of Efficient Reconfigurable Wavelet Filters", Proceedings of the IEEE International Conference on Electro/Information Technology (EIT), May 2008. [PDF]
  60. S. Sun, J. Yan, and J. Zambreno. "Experiments in Attacking FPGA-Based Embedded Systems using Differential Power Analysis", Proceedings of the IEEE International Conference on Electro/Information Technology (EIT), May 2008. [PDF]
  61. A. Das, S. Misra, J. Zambreno, G. Memik, and A. Choudhary. "An Efficient FPGA Implementation of Principle Component Analysis-based Network Intrusion Detection System", Proceedings of Design, Automation, and Test in Europe (DATE), pp. 1160-1165, March 2008. [PDF]
  62. S. Pati, R. Narayanan, G. Memik, A. Choudhary, and J. Zambreno. "Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction", Proceedings of the International Conference on Field-Programmable Technology (FPT), pp. 49-56, December 2007. [PDF]
  63. J. Sathre and J. Zambreno. "Rollback and Huddle: Architectural Support for Trustworthy Application Replay", Proceedings of the Workshop on Embedded Software Security (WESS), October 2007. [PDF]
  64. A. Das, S. Ozdemir, G. Memik, J. Zambreno, and A. Choudhary. "Mitigating the Effects of Process Variations: Architectural Approaches for Improving Batch Performance", Proceedings of the Workshop on Architectural Support for Gigagscale Integration (ASGI), June 2007. [PDF]
  65. R. Narayanan, B. Ozisikyilmaz, G. Memik, A. Choudhary, and J. Zambreno. "Quantization Error and Accuracy-Performance Tradeoffs for Embedded Data Mining Workloads", Proceedings of the International Workshop on High Performance Data Mining (HPDM), May 2007. [PDF]
  66. R. Narayanan, D. Honbo, G. Memik, A. Choudhary, and J. Zambreno. "An FPGA Implementation of Decision Tree Classification", Proceedings of Design, Automation, and Test in Europe (DATE), pp. 189-194, April 2007. [PDF]
  67. A. Choudhary, R. Narayanan, B. Ozisikyilmaz, G. Memik, J. Zambreno, and J. Pisharath. "Optimizing Data Mining Workloads using Hardware Accelerators", Proceedings of the Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), February 2007. [PDF]
  68. B. Ozisikyilmaz, R. Narayanan, J. Zambreno, G. Memik, and A. Choudhary. "An Architectural Characterization Study of Data Mining and Bioinformatics Workloads", Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), pp. 61-70, October 2006. [PDF]
  69. R. Narayanan, B. Ozisikyilmaz, J. Zambreno, G. Memik, and A. Choudhary. "MineBench: A Benchmark Suite for Data Mining Workloads", Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), pp. 182-188, October 2006. [PDF]
  70. R. Simha, B. Narahari, J. Zambreno, and A. Choudhary. "Secure Execution with Components from Untrusted Foundries", Proceedings of the Advanced Networking and Communications Hardware Workshop (ANCHOR), June 2006. [PDF]
  71. J. Pisharath, J. Zambreno, B. Ozisikyilmaz, and A. Choudhary. "Accelerating Data Mining Workloads: Current Approaches and Future Challenges in System Architecture Design", Proceedings of the International Workshop on High Performance Data Mining (HPDM), April 2006. [PDF]
  72. J. Zambreno, B. Ozisikyilmaz, J. Pisharath, G. Memik, and A. Choudhary. "Performance Characterization of Data Mining Applications using MineBench", Proceedings of the Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), February 2006. [PDF]
  73. J. Zambreno, T. Anish, and A. Choudhary. "A Run-Time Reconfigurable Architecture for Embedded Program Flow Verification", Proceedings of the NATO Advanced Research Workshop (ARW) on Security and Embedded Systems, August 2005. [PDF]
  74. O. Gelbart, P. Ott, B. Narahari, R. Simha, A. Choudhary, and J. Zambreno. "CODESSEAL: A Compiler/FPGA Approach to Secure Applications", Proceedings of the IEEE International Conference on Intelligence and Security Informatics (ISI), pp. 530-535, May 2005. [PDF]
  75. K. Mohan, B. Narahari, R. Simha, P. Ott, A. Choudhary, and J. Zambreno. "Performance Study of a Compiler/Hardware Approach to Embedded Systems Security", Proceedings of the IEEE International Conference on Intelligence and Security Informatics (ISI), pp. 543-548, May 2005. [PDF]
  76. J. Zambreno, D. Honbo, and A. Choudhary. "Exploiting Multi-Grained Parallelism in Reconfigurable SBC Architectures", Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 333-334, April 2005. (poster paper) [PDF]
  77. R. Simha, A. Choudhary, B. Narahari, and J. Zambreno. "An Overview of Security-Driven Compilation", Proceedings of the Workshop on New Horizons in Compiler Analysis and Optimizations, December 2004. [PDF]
  78. D. Nguyen, J. Zambreno, and G. Memik. "Flow Monitoring in High-Speed Networks with 2D Hash Tables", Proceedings of the International Conference on Field-Programmable Logic and its Applications (FPL), pp. 1093-1097, August 2004. (poster paper) [PDF]
  79. J. Zambreno, D. Nguyen and A. Choudhary, "Exploring Area/Delay Tradeoffs in an AES FPGA Implementation". Proceedings of the International Conference on Field-Programmable Logic and its Applications (FPL), pp. 575-585, August 2004. [PDF]
  80. J. Zambreno. "Design and Evaluation of an FPGA Architecture for Software Protection", Proceedings of the International Conference on Field-Programmable Logic and its Applications (FPL), p. 1180, August 2004. (poster paper) [PDF]
  81. J. Zambreno, R. Simha, and A. Choudhary. "Addressing Application Integrity Attacks using a Reconfigurable Architecture", Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2004. (poster paper)
  82. J. Zambreno, A. Choudhary, R. Simha, and B. Narahari. "Flexible Software Protection using Hardware/Software Codesign Techniques", Proceedings of Design, Automation, and Test in Europe (DATE), pp. 636-641, February 2004. [PDF]
  83. M. Kandemir, I. Kadayif, A. Choudhary, and J. Zambreno. "Optimizing Inter-nest Data Locality", Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pp. 127-135, October 2002. [PDF]
  84. J. Zambreno, M. Kandemir, and A. Choudhary. "Enhancing Compiler Techniques for Memory Energy Optimizations", Proceedings of the International Conference on Embedded Software (EMSOFT), pp. 364-381, October 2002. [PDF]

Other Papers

  1. J. Zambreno. Compiler and Architectural Approaches to Software Protection and Security. Ph.D. Thesis, Northwestern University, June 2006. [PDF]
  2. J. Zambreno. Enhancing Compiler Techniques for Memory Energy Optimizations. M.S. Thesis, Northwestern University, June 2001. [PDF]