Joseph A. Zambreno
Assistant Professor
Electrical and Computer Engineering
Iowa State University
 |
. | ||
| Address | ECpE Department, Iowa State University 2215 Coover Hall Ames, IA 50011 | ||
| Office | 327 Durham (map) (floorplan) | ||
| Phone | (515) 294-3312 | ||
| Fax | (515) 294-1152 | ||
| zambreno AT iastate DOT edu | |||
Brief Biography
Joseph A. Zambreno has been with the Department of Electrical and Computer Engineering at Iowa State University since 2006, where he is currently an Assistant Professor. Prior to joining ISU he was at Northwestern University in Evanston, IL, where he graduated with his Ph.D. degree in Electrical and Computer Engineering in 2006, his M.S. degree in Electrical and Computer Engineering in 2002, and his B.S. degree summa cum laude in Computer Engineering in 2001. While at Northwestern University, Dr. Zambreno was a recipient of a National Science Foundation Graduate Research Fellowship, a Northwestern University Graduate School Fellowship, a Walter P. Murphy Fellowship, and the EECS department Best Dissertation Award for his Ph.D. dissertation titled "Compiler and Architectural Approaches to Software Protection and Security."
Research Interests
Computer architecture, compilers, embedded systems, and hardware/software co-design, with a focus on run-time reconfigurable architectures and compiler techniques for software protection. More generally, I am interested in reconfigurable computing, including the design and implementation of optimized FPGA architectures in various real-world domains such as cryptography, image and video processing, and data mining.
Selected Recent Publications
- J. Zambreno, D. Honbo, A. Choudhary, R. Simha, and B. Narahari. "High-Performance Software Protection using Reconfigurable Architectures", Proceedings of the IEEE, vol. 94, no. 2, pp. 1-13, February 2006. [PDF]
- D. Nguyen, A. Das, J. Zambreno, G. Memik, and A. Choudhary. "An FPGA-Based Network Intrusion Detection Architecture", IEEE Transactions on Information Forensics and Security (TIFS), vol. 3, no. 1, pp. 118-132, March 2008. [PDF]
- J. Zambreno, A. Choudhary, R. Simha, B. Narahari, and N. Memon. "SAFE-OPS: An Approach to Embedded Software Security, ACM Transactions on Embedded Computing Systems (TECS), vol. 4, no. 1, pp. 189-210, February 2005. [PDF]
- B. Ozisikyilmaz, R. Narayanan, J. Zambreno, G. Memik, and A. Choudhary. "An Architectural Characterization Study of Data Mining and Bioinformatics Workloads", Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), October 2006. [PDF]
- J. Zambreno, D. Nguyen and A. Choudhary, "Exploring Area/Delay Tradeoffs in an AES FPGA Implementation", Proceedings of the International Conference on Field-Programmable Logic and its Applications (FPL), pp. 575-585, August 2004. [PDF]
 |
Copyright © 2008 by Joseph Zambreno. All rights reserved. |