Title: A Cache Architecture for Mixed Criticality Real-Time Systems
Speaker: Chetan Kumar, ECpE Graduate Student
Advisor: Phillip Jones, Assistant Professor
Abstract: As recent trends in real-time and embedded systems show, applications of different criticality are being executed on a single hardware platform driven by the need to reduce size, cost and power requirements. In these mixed criticality real-time systems, it is necessary to provide spacial and temporal isolation guarantees for critical tasks to ensure their timing constraints are met under all conditions. While state-of-the-art research in mixed criticality systems focuses on CPU and its scheduling, often the most unpredictable aspect of a platform is not the CPU, but other components such as storage hierarchy. Inter-task cache conflicts in mixed criticality systems is one such source of unpredictability that can affect the performance and response time of critical tasks and lead to WCET pessimism. I present a criticality aware cache architecture for mixed criticality real-time systems, to mitigate inter-task interference arising from critical tasks sharing cache with non-critical tasks. As a part of the proposed cache design, a new cache replacement policy called Least Critical (LC) is presented, where critical tasks’ data is least likely to be evicted from the cache. Experimental results illustrate the impact of the LC cache replacement policy on the response time of critical tasks, and on overall application performance.